Read e-book online Algorithms and Techniques for VLSI Layout Synthesis PDF

By Dwight Hill, Don Shugard, John Fishburn, Kurt Keutzer

ISBN-10: 1461289629

ISBN-13: 9781461289623

ISBN-10: 146131707X

ISBN-13: 9781461317074

This e-book describes a approach of VLSI format instruments referred to as IDA which stands for "Integrated layout Aides. " it's not a main-line creation CAD atmosphere, yet nor is it a paper device. quite, IDA is an experimental surroundings that serves to check out CAD principles within the crucible of actual chip layout. Many gains were attempted in IDA through the years, a few effectively, a few no longer. This publication will emphasize the previous, and try and describe the gains which have been worthwhile and powerful in development actual chips. sooner than discussing the current kingdom of IDA, it can be worthy to appreciate how the undertaking obtained began. even though Bell Labs has ordinarily had a wide and potent attempt in VLSI and CAD, researchers on the Murray Hill facility desired to examine the method of VLSI layout independently, emphasizing the assumption of small crew chip construction. So, in 1979 they invited Carver Mead to offer his perspectives on MOS chip layout, entire with the now recognized "lambda" layout principles and "tall, skinny designers. " To aid this direction, Steve Johnson (better recognized for YACC and the transportable C compiler) and Sally Browning invented the constraint­ dependent "i" language and wrote a compiler for it. A small selection of format instruments built speedily round this compiler, together with layout rule checkers, editors and simulators.

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If several wires appear under the cursor, the editor selects one arbitrarily, and reissuing the command rotates among them. The user can also identify regions delimited by the cursor and the mark. Objects can be put in the chosen group either inclusive or exclusive of wires passing through the boundaries. g. ). This relationship is shown in Figure 3-2. J Figure 3-2: Manipulation of the Chosen Group. Once the chosen group has been selected it is highlighted on the screen. The contents of the group of chosen features can then be adjusted by picking one or more items using a menu or by using the "filter" command.

An example of this is the "filter chip" schematic shown in Figure 3-6. This chip consists of a large shift register (in the lower right) combined with an address storage and recognition unit (in the upper left). The shift register was considered so simple schematically that no logic diagram was ever made for it. Rather, a layout was produced semi-automatically by a shift-register layout generator. Then the layout was included into the schematic for the overall chip.

The The IMAGES Language 27 problem with the graph in Figure 2-8 is that only vertex ZERO has an initial value. Using Algorithm 2-4 we would initially solve the subgraph consisting of the positive edges then add in the negative edges. However, because the root of the positive subgraph (vertex Z) is unconstrained, following the topological ordering of the positive sub graph would not result in solving the constraints. Previously we avoided this problem by requiring Z to be constrained, either by an equality constraint such as Z = 5 or an inequality constraint such as Z ~ 5.

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Algorithms and Techniques for VLSI Layout Synthesis by Dwight Hill, Don Shugard, John Fishburn, Kurt Keutzer

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